Specifications
Figure 9-2: User I/O BSC with IEEE Std. 1149.1 BST Circuitry for Cyclone V Devices
0
1
OUTPUT
OE
INPUTINPUT
OUTPUT
OE
From or
To Device
I/O Cell
Circuitry
And/Or
Logic
Array
0
1
0
1
0
1
0
1
0
1
0
1
PIN_OUT
INJ
OEJ
OUTJ
VCC
SDO
Pin
SHIFT
SDI
CLOCK HIGHZ MODE
PIN_OE
PIN_IN
Output
Buffer
Capture
Registers
Update
Registers
Global
Signals
UPDATE
D Q
D Q
D Q D Q
D Q
D Q
TDI, TDO, TMS, and TCK pins, all VCC and GND pin types, and VREF pins do not have BSCs.
Note:
Table 9-5: Boundary-Scan Cell Descriptions for Cyclone V Devices
This table lists the capture and update register capabilities of all BSCs within Cyclone V devices.
Comments
DrivesCaptures
Pin Type
Input
Update
Register
OE Update
Register
Output
Update
Register
Input
Capture
Register
OE Capture
Register
Output
Capture
Register
—
INJPIN_OEPIN_OUTPIN_INOEJOUTJ
User I/O pins
PIN_IN
drives to the
clock network
or logic array
N.C.N.C.No
Connect
(N.C.)
PIN_IN
10Dedicated
clock input
PIN_IN
drives to the
control logic
N.C.N.C.N.C.
PIN_IN
10Dedicated
input
(22)
(22)
This includes the PLL_ENA, VCCSEL, PORSEL, nIO_PULLUP, nCONFIG, MSEL0, MSEL1, MSEL2, MSEL3,
MSEL4, and nCE pins.
JTAG Boundary-Scan Testing in Cyclone V Devices
Altera Corporation
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CV-52009
Boundary-Scan Cells of a Cyclone V Device I/O Pin
9-10
2013.05.06