Specifications

DescriptionInstruction CodeJTAG Instruction
• Places the 1-bit bypass register
between the TDI and TDO pins.
During normal operation, the 1-bit
bypass register allows the BST data
to pass synchronously through the
selected devices to adjacent devices
while holding the I/O pins to a state
defined by the data in the
boundary-scan register.
• If you are testing the device after
configuration, the programmable
weak pull-up resistor or the bus
hold feature overrides the CLAMP
value at the pin. The CLAMP value
is the value stored in the update
register of the boundary-scan cell
(BSC).
00 0000 1010
CLAMP
Emulates pulsing the nCONFIG pin
low to trigger reconfiguration even
though the physical pin is not affected.
00 0000 0001
PULSE_NCONFIG
Allows I/O reconfiguration (after or
during reconfigurations) through the
JTAG ports using I/O configuration
shift register (IOCSR) for JTAG testing.
You can issue the CONFIG_IO
instruction only after the nSTATUS
pin goes high.
00 0000 1101
CONFIG_IO
Put the device in JTAG secure mode.
In this mode, only BYPASS, SAMPLE/
PRELOAD, EXTEST, IDCODE,
SHIFT_EDERROR_REG, and UNLOCK
instructions are supported. This
instruction can only be accessed
through JTAG core access in user
mode. It cannot be accessed through
external JTAG pins in test or user
mode.
01 1111 0000
LOCK
Release the device from the JTAG
secure mode to enable access to all
other JTAG instructions. This instruc-
tion can only be accessed through
JTAG core access in user mode. It
cannot be accessed through external
JTAG pins in test or user mode.
11 0011 0001
UNLOCK
Clears the non-volatile key.00 0010 1001
KEY_CLR_VREG
Verifies the non-volatile key has been
cleared.
00 0001 0011
KEY_VERIFY
Altera Corporation
JTAG Boundary-Scan Testing in Cyclone V Devices
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9-5
Supported JTAG Instruction
CV-52009
2013.05.06