Specifications

DescriptionMemory TypeOutput Mode
The RAM outputs dont care or unknown value. The
Quartus II software analyzes the timing between write and
read operations in the MLAB.
MLAB"constrained don't care"
Figure 2-3: Mixed-Port Read-During-Write: New Data Mode
This figure shows a sample functional waveform of mixed-port read-during-write behavior for the new
data mode.
XXXX
11
clk_a&b
address_a
wren_a
byteena_a
rden_b
data_a
q_b (registered)
address_b
AAAA BBBB CCCC DDDD EEEE FFFF
A0 A1
A0 A1
AAAA BBBB CCCC DDDD EEEE FFFF
Figure 2-4: Mixed-Port Read-During-Write: Old Data Mode
This figure shows a sample functional waveform of mixed-port read-during-write behavior for the old data
mode.
clk_a&b
address_a
wren_a
byteena_a
rden_b
data_a
q_b (asynch)
address_b
A0 A1
AAAA BBBB CCCC DDDD
EEEE
FFFF
11
A0 A1
A0 (old data)
AAAA BBBB DDDD EEEE
A1 (old data)
Altera Corporation
Embedded Memory Blocks in Cyclone V Devices
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2-5
Mixed-Port Read-During-Write Mode
CV-52002
2013.05.06