Specifications

comes last. Therefore, you can start retrieving the contents of the EMR at the rising edge of the CRC_ERROR
pin. The pin stays high until the current frame is read and then driven low again for a minimum of 32 clock
cycles. To ensure information integrity, complete the read operation within one frame of the CRC verification.
The following diagram shows the timing of these events.
Figure 8-5: Timing Requirements
No CRC Error CRC Error
CRC Error
CRC ErrorNo CRC Error No CRC Error
N N+1 N+2 N+3 N+4 N+5
Frame
Data Integrity
Read Data Frame
CRC ERROR Pin
CRC Calculation
(minimum 32 clock
cycles)
Read Error Message
Register (allowed time)
Read Error Message
for frame N+1
Read Error Message
for frame N+2
Read Error Message
for frame N+4
Retrieving Error Information
You can retrieve the error information via the core interface or the JTAG interface using the
SHIFT_EDERROR_REG JTAG instruction.
Recovering from CRC Errors
The system that hosts the FPGA must control device reconfiguration. To recover from a CRC error, drive
the nCONFIG signal low. The system waits for a safe time before reconfiguring the device. When reconfig-
uration completes successfully, the FPGA operates as intended.
Related Information
• Error Detection Frequency on page 8-3
Provides more information about the minimum and maximum error detection frequencies.
• Minimum EMR Update Interval on page 8-2
Provides more information about the duration of each Cyclone Vdevice.
• Test Methodology of Error Detection and Recovery using CRC in Altera FPGA Devices
Provides more information about how to retrieve the error information.
Testing the Error Detection Block
You can inject errors into the configuration data to test the error detection block. This error injection
methodology provides design verification and system fault tolerance characterization.
Testing via the JTAG Interface
You can intentionally inject single or double-adjacent errors into the configuration data using the
EDERROR_INJECT JTAG instruction.
SEU Mitigation for Cyclone V Devices
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Testing the Error Detection Block
8-8
2013.11.12