Specifications

Table 8-6: Error Type in EMR
The following table lists the possible error types reported in the error type field in the EMR.
Description
Error Type
Bit 0Bit 1Bit 2Bit 3
No CRC error.0000
Location of a single-bit error is identified.1000
Location of a double-adjacent error is identified.0100
Error types other than single-bit and double-adjacent errors.1111
Table 8-7: JTAG Fault Injection Register Map
DescriptionBit RangeField Name
Contains the location of the bit error that
corresponds to the error injection type to this
field.
31:0Error Byte
Value
Contains the location of the injected error in
the first data frame.
41:32Byte Location
Specifies the following error types.
45:42
Error Type
Bit 42Bit 43Bit 44Bit 45
No error0000
Single-bit error1000
Double adjacent error0100
Error Detection Process
When enabled, the user mode error detection process activates automatically when the FPGA enters user
mode. The process continues to run until the device is reset even when an error is detected in the current
frame.
Figure 8-4: Error Detection Process Flow in User Mode
Yes
No
Receive
Data Frame
Calculate and
Compare
CRC Values
Error
Detected?
Pull CRC_ERROR
Signal Low for
32 Clock Cycles
Update Error
Message Register
(Overwrite)
Search for
Error Location
Drive
CRC_ERROR
Signal High
Timing
The CRC_ERROR pin is always driven low during CRC calculation for a minimum of 32 clock cycles. When
an error occurs, the pin is driven high once the EMR is updated or 32 clock cycles have lapsed, whichever
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SEU Mitigation for Cyclone V Devices
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8-7
Error Detection Process
CV-52008
2013.11.12