Specifications

Table 8-5: Error Detection Registers
DescriptionWidth (Bits)Name
Contains the 32-bit CRC signature calculated for the current
frame. If the CRC value is 0, the CRC_ERROR pin is driven
low to indicate no error. Otherwise, the pin is pulled high.
32Syndrome register
Contains error details for single-bit and double-adjacent
errors. The error detection circuitry updates this register
each time the circuitry detects an error. Figure 8-3 shows
the fields in this register and Table 8-6 lists the possible error
types.
67Error message register (EMR)
This register is automatically updated with the contents of
the EMR one clock cycle after the content of this register is
validated. The JTAG update register includes a clock enable,
which must be asserted before its contents are written to the
JTAG shift register. This requirement ensures that the JTAG
update register is not overwritten when its contents are being
read by the JTAG shift register.
67JTAG update register
This register allows you to access the contents of the JTAG
update register via the JTAG interface using the SHIFT_
EDERROR_REG JTAG instruction.
67JTAG shift register
This register is automatically updated with the contents of
the EMR one clock cycle after the contents of this register
are validated. The user update register includes a clock
enable, which must be asserted before its contents are written
to the user shift register. This requirement ensures that the
user update register is not overwritten when its contents are
being read by the user shift register.
67User update register
This register allows user logic to access the contents of the
user update register via the core interface.
67User shift register
You can use this register with the EDERROR_INJECT
JTAG instruction to inject errors in the bitstream. Table 8-
7 lists the fields in this register.
46JTAG fault injection register
This register is updated with the contents of the JTAG fault
injection register.
46Fault injection register
Figure 8-3: Error Message Register Map
Syndrome Frame Address Byte Offset Bit Offset Error Type
MSB LSB
32 bits 16 bits 10 bits 2 bits 3 bits 4 bits
Double Word
Location
SEU Mitigation for Cyclone V Devices
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Error Detection Registers
8-6
2013.11.12