Specifications

Timing Interval (µs)Member CodeVariant
1.79D5
Cyclone V GT 2.33D7
3.23D9
1.77A2
Cyclone V SE
1.77A4
2.31A5
2.31A6
1.77C4
Cyclone V SX 2.31C5
2.31C6
2.31D5
Cyclone V ST
2.31D6
Error Detection Frequency
You can control the speed of the error detection process by setting the division factor of the clock frequency
in the Quartus II software. The divisor is 2
n
, where n can be any value listed in the following table.
The speed of the error detection process for each data frame is determined by the following equation:
Figure 8-1: Error Detection Frequency Equation
Error Detection Frequency =
Internal Oscillator Frequency
2
n
Table 8-2: Error Detection Frequency Range for Cyclone V Devices
The following table lists the frequencies and valid values of n.
Divisor Rangen
Error Detection Frequency
Internal Oscillator Frequency
MinimumMaximum
1 – 2560, 1, 2, 3, 4, 5, 6, 7, 8390 kHz100 MHz100 MHz
CRC Calculation Time
The time taken by the error detection circuitry to calculate the CRC for each frame is determined by the
device in use and the frequency of the error detection clock.
You can calculate the minimum and maximum time for any number of divisor based on the following
formula:
Maximum time (n) = 2^(n-8) * maximum time
Minimum time (n) = 2^n * minimum time
where the range of n is from 0 to 8.
Altera Corporation
SEU Mitigation for Cyclone V Devices
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8-3
Error Detection Frequency
CV-52008
2013.11.12