Specifications

Figure 2-2: Same-Port Read-During-Write: New Data Mode
This figure shows sample functional waveforms of same-port read-during-write behavior in the “new data”
mode.
clk_a
address
rden
wren
byteena
data_a
q_a (asynch)
A123
B456
C789
DDDD EEEE FFFF
A123 B456 C789 DDDD EEEE FFFF
0A 0B
11
Mixed-Port Read-During-Write Mode
The mixed-port read-during-write mode applies to simple and true dual-port RAM modes where two ports
perform read and write operations on the same memory address using the same clock—one port reading
from the address, and the other port writing to it.
Table 2-3: Output Modes for RAM in Mixed-Port Read-During-Write Mode
DescriptionMemory TypeOutput Mode
A read-during-write operation to different ports causes the
MLAB registered output to reflect the “new data” on the
next rising edge after the data is written to the MLAB
memory.
This mode is available only if the output is registered.
MLAB"new data"
A read-during-write operation to different ports causes the
RAM output to reflect the “old data” value at the particular
address.
For MLAB, this mode is available only if the output is
registered.
M10K, MLAB"old data"
The RAM outputs “don’t care” or “unknown” value.
• For M10K memory, the Quartus II software does not
analyze the timing between write and read operations.
• For MLAB, the Quartus II software analyzes the timing
between write and read operations by default. To disable
this behavior, turn on the Do not analyze the timing
between write and read operation. Metastability issues
are prevented by never writing and reading at the
same address at the same time option.
M10K, MLAB"don't care"
Embedded Memory Blocks in Cyclone V Devices
Altera Corporation
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Mixed-Port Read-During-Write Mode
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2013.05.06