Specifications

1. After power-up, the remote system upgrade registers are reset to 0 and the factory configuration image
is loaded.
2.
The user logic sets the AnF bit to 1 and the start address of the application image to be loaded. The user
logic also writes the watchdog timer settings.
3.
When the configuration reset (RU_CONFIG) goes low, the state machine updates the control register
with the contents of the update register, and triggers reconfiguration using the application configuration
image.
4. If error occurs, the state machine falls back to the factory image. The control and update registers are
reset to 0, and the status register is updated with the error information.
5. After successful reconfiguration, the system stays in the application configuration.
User Watchdog Timer
The user watchdog timer prevents a faulty application configuration from stalling the device indefinitely.
You can use the timer to detect functional errors when an application configuration is successfully loaded
into the device. The timer is automatically disabled in the factory configuration; enabled in the application
configuration.
If you do not want this feature in the application configuration, you need to turn off this feature by
setting the Wd_en bit to 1'b0 in the update register during factory configuration user mode operation.
You cannot disable this feature in the application configuration.
Note:
The counter is 29 bits wide and has a maximum count value of 2
29
. When specifying the user watchdog timer
value, specify only the most significant 12 bits. The granularity of the timer setting is 2
17
cycles. The cycle
time is based on the frequency of the user watchdog timer internal oscillator.
The timer begins counting as soon as the application configuration enters user mode. When the timer expires,
the remote system upgrade circuitry generates a time-out signal, updates the status register, and triggers the
loading of the factory configuration image. To reset the time, assert RU_nRSTIMER.
Related Information
Cyclone V Device Datasheet
Provides more information about the operating range of the user watchdog internal oscillator's frequency.
Design Security
The Cyclone V design security feature supports the following capabilities:
• Enhanced built-in advanced encryption standard (AES) decryption block to support 256-bit key
industry-standard design security algorithm (FIPS-197 Certified)
• Volatile and non-volatile key programming support
• Secure operation mode for both volatile and non-volatile key through tamper protection bit setting
• Limited accessible JTAG instruction during power-up in the JTAG secure mode
• Supports board-level testing
• Supports in-socket key programming for non-volatile key
• Available in all configuration schemes except JTAG
• Supports both remote system upgrades and compression features
The Cyclone V design security feature provides the following security protection for your designs:
Altera Corporation
Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
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User Watchdog Timer
CV-52007
2013.06.11