Specifications

Figure 7-17: JTAG Configuration of a Single Device Using a Download Cable
Download Cable
10-Pin Male Header
(JTAG Mode) (Top View)
FPGA Device
DCLK
nCONFIG
CONF_DONE
GNDGND
nSTATUS
TDI
TMS
TDO
TCK
Pin 1
nCE
GND
GND
nCEON.C.
MSEL[4..0]
V
CCPGM
V
CCPGM
10 kΩ 10 kΩ
V
CCPD
1 kΩ
Connect the pull-up
resistor V
CCPD
.
If you only use the JTAG configuration, connect
nCONFIG to V
CCPGM
and MSEL[4..0] to GND.
Pull DCLK either high or low whichever is
convenient on your board. If you are using JTAG
in conjunction with another configuration scheme,
connect MSEL[4..0], nCONFIG, and DCLK based
on the selected configuration scheme.
The resistor value can vary
from 1 kΩ to 10 kΩ. Perform
signal integrity analysis to
select the resistor value for
your setup.
V
CCPD
V
CCPD
To configure a Cyclone V device using a microprocessor, connect the device as shown in the following figure.
You can use JRunner as your software driver.
Figure 7-18: JTAG Configuration of a Single Device Using a Microprocessor
Microprocessor
CONF_DONE
nSTATUS
nCE
nCONFIG
FPGA Device
Memory
ADDR
GND
DCLK
TDI
TCK
TMS
nCEO
N.C.
MSEL[4..0]
DATA
TDO
10 kΩ10 kΩ
V
CCPGM
Connect the pull-up resistor to a supply that
provides an acceptable input signal for all
FPGA devices in the chain. V
CCPGM
must be
high enough to meet the V
IH
specification of
the I/O on the device.
If you only use the JTAG configuration,
connect nCONFIG to V
CCPGM
and
MSEL[4..0] to GND. Pull DCLK high or
low. If you are using JTAG in conjunction
with another configuration scheme, set
the MSEL[4..0] pins and tie nCONFIG and
DCLK based on the selected
configuration scheme.
The microprocessor must use
the same I/O standard as
V
CCPD
to drive the JTAG pins.
V
CCPGM
Related Information
AN 414: The JRunner Software Driver: An Embedded Solution for PLD JTAG Configuration
Altera Corporation
Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
Send Feedback
7-25
JTAG Single-Device Configuration
CV-52007
2013.06.11