Specifications

The nCE pins of the devices in the chain are connected to GND, allowing configuration for these devices to
begin and end at the same time.
Using PC Host and Download Cable
To configure multiple Cyclone V devices, connect the devices to a download cable, as shown in the following
figure.
Figure 7-16: Multiple Device PS Configuration Using an Altera Download Cable
FPGA Device 1
FPGA Device 2
nCE
nCONFIG
CONF_DONE
DCLK
nCE
nCONFIG
CONF_DONE
DCLK
nCEO
GND
(PS Mode)
V
CCPGM
V
CCPGM
V
CCPGM
V
CCPGM
V
CCPGM
nSTATUS
nSTATUS
DATA0
DATA0
GND
10 kΩ
10 kΩ
Pin 1
Download Cable
10-Pin Male Header
nCEO N.C.
GND
V
IO
MSEL[4..0]
MSEL[4..0]
V
CCPGM
10 kΩ
10 kΩ
10 kΩ (2)
Connect the pull-up resistor to the
same supply voltage (V
CCIO
) as the
USB-Blaster, ByteBlaster II,
EthernetBlaster, or EthernetBlaster II
cable.
You only need the pull-up resistors on
DATA0 and DCLK if the download cable
is the only configuration scheme used
on your board. This ensures that
DATA0 and DCLK are not left floating
after configuration. For example, if you
are also using a configuration device,
you do not need the pull-up resistors on
DATA0 and DCLK.
In the USB-Blaster and
ByteBlaster II cables, this
pin is connected to nCE
when you use it for AS
programming. Otherwise,
this pin is a no connect.
For more information, refer to
the MSEL pin settings.
When a device completes configuration, its nCEO pin is released low to activate the nCE pin of the next
device. Configuration automatically begins for the second device.
JTAG Configuration
In Cyclone V devices, JTAG instructions take precedence over other configuration schemes.
The Quartus II software generates an SRAM Object File (.sof) that you can use for JTAG configuration using
a download cable in the Quartus II software programmer. Alternatively, you can use the JRunner software
with .rbf or a JAM
™
Standard Test and Programming Language (STAPL) Format File (.jam) or JAM Byte
Code File (.jbc) with other third-party programmer tools.
Related Information
• JTAG Boundary-Scan Testing in Cyclone V Devices on page 9-1
Provides more information about JTAG boundary-scan testing.
• Device Configuration Pins on page 7-6
Provides more information about JTAG configuration pins.
Altera Corporation
Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
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7-23
Using PC Host and Download Cable
CV-52007
2013.06.11