Specifications

Total RAM Bit (Kb)
MLABM10K
Member
CodeVariant RAM Bit (Kb)BlockRAM Bit (Kb)Block
1,3491592551,190119C3
Cyclone V GX
2,7952954722,500250C4
4,8844246794,460446C5
7,69683613386,860686C7
13,9171,717274812,2001,220C9
4,8844246794,460446D5
Cyclone V GT 7,69683613386,860686D7
13,9171,717274812,2001,220D9
1,5381382211,400140A2
Cyclone V SE
2,4602313702,700270A4
4,4504807683,970397A5
5,7616219945,570557A6
1,5381382211,400140C2
Cyclone V SX
2,4602313702,700270C4
4,4504807683,970397C5
5,7616219945,570557C6
4,4504807683,970397D5
Cyclone V ST
5,7616219945,570557D6
Embedded Memory Design Guidelines for Cyclone V Devices
There are several considerations that require your attention to ensure the success of your designs. Unless
noted otherwise, these design guidelines apply to all variants of this device family.
Guideline: Consider the Memory Block Selection
The Quartus II software automatically partitions the user-defined memory into the memory blocks based
on your design's speed and size constraints. For example, the Quartus II software may spread out the memory
across multiple available memory blocks to increase the performance of the design.
To assign the memory to a specific block size manually, use the RAM megafunction in the MegaWizard
™
Plug-In Manager.
For the memory logic array blocks (MLAB), you can implement single-port SRAM through emulation using
the Quartus II software. Emulation results in minimal additional use of logic resources.
Because of the dual-purpose architecture of the MLAB, only data input and output registers are available in
the block. The MLABs gain read address registers from the ALMs. However, the write address and read data
registers are internal to the MLABs.
Embedded Memory Blocks in Cyclone V Devices
Altera Corporation
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Embedded Memory Design Guidelines for Cyclone V Devices
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2013.05.06