Specifications

The maximum DCLK frequency supported by the AS configuration scheme is 100 MHz except for the AS
multi-device configuration scheme. You can source DCLK using CLKUSR or the internal oscillator. If you
use the internal oscillator, you can choose a 12.5, 25, 50, or 100 MHz clock under the Device and Pin Options
dialog box, in the Configuration page of the Quartus II software.
After power-up, DCLK is driven by a 12.5 MHz internal oscillator by default. The Cyclone V device determines
the clock source and frequency to use by reading the option bit in the programming file.
Related Information
Cyclone V Device Datasheet
Provides more information about the DCLK frequency specification in the AS configuration scheme.
Active Serial Single-Device Configuration
To configure a Cyclone V device, connect the device to a serial configuration (EPCS) device or quad-serial
configuration (EPCQ) device, as shown in the following figures.
Figure 7-5: Single Device AS x1 Mode Configuration
DATA
DCLK
nCS
ASDI
AS_DATA1
DCLK
nCSO
ASDO
EPCS or EPCQ Device FPGA Device
10 kΩ10 kΩ10 kΩ
V
CCPGM
GND
nCEO
nCE
nSTATUS
nCONFIG
CONF_DONE
N.C.
MSEL[4..0]
CLKUSR
V
CCPGM
V
CCPGM
Connect the pull-up resistors to
V
CCPGM
at 3.0- or 3.3-V power supply.
For more information,
refer to the MSEL pin
settings.
Use the CLKUSR pin to
supply the external clock
source to drive DCLK
during configuration.
Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
Altera Corporation
Send Feedback
CV-52007
Active Serial Single-Device Configuration
7-12
2013.06.11