Specifications

When a device completes configuration, its nCEO pin is released low to activate the nCE pin of the next
device in the chain. Configuration automatically begins for the second device in one clock cycle.
Using One Configuration Data
To configure multiple Cyclone V devices in a chain using one configuration data, connect the devices to an
external host as shown in the following figure.
Figure 7-4: Multiple Device FPP Configuration Using an External Host When Both Devices Receive the Same
Data
nCONFIG
Memory
ADDR DATA[7..0]
DCLK
nCEO
N.C.
nCONFIG
DCLK
nCEO
N.C.
MSEL[4..0]
MSEL[4..0]
V
CCPGM
V
CCPGM
10 kΩ
10 kΩ
GND GND
CONF_DONE CONF_DONE
nSTATUS nSTATUS
nCE
nCE
DATA[]
DATA[]
Buffers
External Host
(MAX II Device,
MAX V Device, or
Microprocessor)
FPGA Device Master
FPGA Device Slave
Connect the resistor to a supply that
provides an acceptable input signal for the
FPGA device. V
CCPGM
must be high
enough to meet the V
IH
specification of
the I/O on the device and the external
host. Altera recommends powering up all
configuration system I/Os with V
CCPGM
.
For more information, refer to
the MSEL pin settings.
You can leave the nCEO pin
unconnected or use it as a user
I/O pin when it does not feed
another device’s nCE pin.
Connect the repeater buffers between the
FPGA master and slave device for DATA[]
and DCLK for every fourth device.
The nCE pins of the device in the chain are connected to GND, allowing configuration for these devices to
begin and end at the same time.
Active Serial Configuration
The AS configuration scheme supports AS x1 (1-bit data width) and AS x4 (4-bit data width) modes. The
AS x4 mode provides four times faster configuration time than the AS x1 mode. In the AS configuration
scheme, the Cyclone V device controls the configuration interface.
Related Information
Cyclone V Device Datasheet
Provides more information about the AS configuration timing.
DATA Clock (DCLK)
Cyclone V devices generate the serial clock, DCLK, that provides timing to the serial interface. In the AS
configuration scheme, Cyclone V devices drive control signals on the falling edge of DCLK and latch the
configuration data on the following falling edge of this clock pin.
Altera Corporation
Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
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7-11
Using One Configuration Data
CV-52007
2013.06.11