Specifications

Table 7-1: Configuration Modes and Features Supported by Cyclone V Devices
Remote System
Update
Partial
Reconfigura-
tion
(14)
Design
Security
Decompres-
sion
Max Data
Rate
(Mbps)
Max Clock
Rate
(MHz)
Data
Width
Mode
Yes—YesYes—1001 bit, 4
bits
AS through the
EPCS and EPCQ
serial configura-
tion device
——YesYes1251251 bitPS through CPLD
or external
microcontroller
Parallel flash loader
—YesYes—1258 bits
FPP
YesYesYes—12516 bits
—YesYes———x1, x2,
and x4
lanes
CvP (PCIe)
————33331 bitJTAG
Instead of using an external flash or ROM, you can configure the Cyclone V devices through PCIe using
CvP. The CvP mode offers the fastest configuration rate and flexibility with the easy-to-use PCIe hard IP
block interface. The Cyclone V CvP implementation conforms to the PCIe 100 ms power-up-to-active time
requirement.
Related Information
Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide
Provides more information about the CvP configuration scheme.
MSEL Pin Settings
To select a configuration scheme, hardwire the MSEL pins to V
CCPGM
or GND without pull-up or pull-down
resistors.
Do not drive the MSEL pins with a microprocessor or another device.
Note:
(14)
Partial reconfiguration is an advanced feature of the device family. If you are interested in using partial
reconfiguration, contact Altera for support.
Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
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MSEL Pin Settings
7-2
2013.06.11