Specifications

ChangesVersionDate
• Added the I/O and DQS configuration blocks topic.
• Updated the term "Multiport logic" to "multi-port front end" (MPFE).
• Added information about the hard memory controller interface widths
for the Cyclone V E, GX, GT, SX, and ST variants.
Updated for the Quartus II software v12.0 release:
• Restructured chapter.
• Updated “Design Considerations”, “DQS Postamble Circuitry”, and
“IOE Registers”sections.
• Added SoC devices information.
• Added Figure 6–5, Figure 6–10, and Figure 6–21.
2.0June 2012
• Updated Figure 6–20.
• Minor text edits.
1.2February 2012
• Updated Table 6–2.
• Added Figure 6–2.
1.1November 2011
Initial release.1.0October 2011
External Memory Interfaces in Cyclone V Devices
Altera Corporation
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Document Revision History
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2013.05.06