Specifications

Figure 6-24: Hard Memory Controllers in Cyclone V SX C2, C4, C5, and C6 Devices, and Cyclone V ST D5 and
D6 Devices
This figure shows hard memory controllers in the SoC FPGAs. There is no bonding support.
Bank 8A
HPS I/OBank 5
HPS I/O
HPS Block
HPS Hard Memory Controller
32-bit DDR3 Interface
32-bit Interface
Bank 4A
Bank 3A Bank 3B
Hard Memory Controller
Related Information
Cyclone V Device Family Pin Connection Guidelines
Provides more information about the dedicated pins.
Hard Memory Controller Width for Cyclone V E
Table 6-15: Hard Memory Controller Width Per Side in Cyclone V E Devices—Preliminary
Member Code
Package A9A7A5A4A2
BottomTopBottomTopBottomTopBottomTopBottomTop
————0≤ 240≤ 240≤ 24M383
——2424——————M484
——————0000F256
——————0000U324
——24242424024024U484
External Memory Interfaces in Cyclone V Devices
Altera Corporation
Send Feedback
CV-52006
Hard Memory Controller Width for Cyclone V E
6-34
2013.05.06