Specifications

DescriptionFeature
You can select the region of memory to refresh during self-refresh through the mode
register to save power.
Partial Array Self-
Refresh
Standard Hamming single error correction, double error detection (SECDED) error
correction code (ECC) support:
• 32 bit data + 8 bit ECC
• 16 bit data + 8 bit ECC
ECC
With additive latency, the controller can issue a READ/WRITE command after the
ACTIVATE command to the bank prior to t
RCD
to increase the command efficiency.
Additive Latency
The controller supports write acknowledgment on the local interface.Write Acknowledg-
ment
The controller supports initialization of the memory controller under the control of
user logic—for example, through the software control in the user system if a processor
is present.
User Control of
Memory Controller
Initialization
You can bond two controllers to achieve wider data width for higher bandwidth
applications.
Controller Bonding
Support
Multi-Port Front End
The multi-port front end (MPFE) and its associated fabric interface provide up to six command ports, four
read-data ports and four write-data ports, through which user logic can access the hard memory controller.
Figure 6-22: Simplified Diagram of the Cyclone V Hard Memory Interface
This figure shows a simplified diagram of the Cyclone V hard memory interface with the MPFE.
MPFE
Memory
Controller
PHY
Memory
FPGA
Core Logic
FPGA
Avalon-MM Interface
AFI
Altera Corporation
External Memory Interfaces in Cyclone V Devices
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Multi-Port Front End
CV-52006
2013.05.06