Specifications

Figure 6-21: Configuration Block (I/O and DQS)
This figure shows the I/O configuration block and the DQS configuration block circuitry.
datain
bit0bit1bit2MSB
dataout
update
ena
clk
rankselectread
rankselectwrite
Related Information
ALTDQ_DQS2 Megafunction User Guide
Provides details about the I/O and DQS configuration block bit sequence.
Hard Memory Controller
The Cyclone V devices feature dedicated hard memory controllers. You can use the hard memory controllers
for LPDDR2, DDR2, and DDR3 SDRAM interfaces. Compared to the memory controllers implemented
using core logic, the hard memory controllers allow support for higher memory interface frequencies with
shorter latency cycles.
The hard memory controllers use dedicated I/O pins as data, address, command, control, clock, and ground
pins for the SDRAM interface. If you do not use the hard memory controllers, you can use these dedicated
pins as regular I/O pins.
Related Information
• Functional Description—HPC II Controller chapter, External Memory Interface Handbook
The hard memory controller is functionally similar to the High-Performance Controller II (HPC II).
• Functional Description—Hard Memory Interface chapter, External Memory Interface Handbook
Provides detailed information about application of the hard memory interface.
Features of the Hard Memory Controller
Table 6-13: Features of the Cyclone V Hard Memory Controller
DescriptionFeature
• 8, 16, and 32 bit data
• 16 bit data + 8 bit ECC
• 32 bit data + 8bit ECC
Memory Interface
Data Width
The controller supports up to four gigabits density parts and two chip selects.Memory Density
Altera Corporation
External Memory Interfaces in Cyclone V Devices
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Hard Memory Controller
CV-52006
2013.05.06