Specifications

Figure 6-19: Delay Chains in an I/O Block
D5 OCT
delay
chain
OCT Enable
Output Enable
D5
output-enable
delay chain
D5 Delay
delay
chain
D1 Delay
delay chain
0
1
DQ or DQS
Each DQS logic block contains a delay chain after the dqsbusout output and another delay chain before
the dqsenable input.
Figure 6-20: Delay Chains in the DQS Input Path
DQS
Enable
dqsin
dqsenable
DQS
Enable
Control
DQS delay
chain
D4
delay
chain
dqsbusout
DQS
T11
delay
chain
I/O and DQS Configuration Blocks
The I/O and DQS configuration blocks are shift registers that you can use to dynamically change the settings
of various device configuration bits.
• The shift registers power-up low.
• Every I/O pin contains one I/O configuration register.
• Every DQS pin contains one DQS configuration block in addition to the I/O configuration register.
External Memory Interfaces in Cyclone V Devices
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I/O and DQS Configuration Blocks
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2013.05.06