Specifications

Figure 6-18: IOE Output and Output-Enable Path Registers for Cyclone V Devices
The following figure shows the registers available in the Cyclone V output and output-enable paths.
DFF
D
Q
OE Reg A
OE
DFF
D
Q
OE Reg B
OE
1
0
1
0
DFF
D
Q
DFF
D
Q
Half Data Rate to Single
Data Rate Output-Enable
Registers
Double Data Rate
Output-Enable Registers
1
0
DFF
D
Q
DFF
D
Q
Half Data Rate to Single
Data Rate Output Registers
1
0
DFF
D
Q
DFF
D
Q
From Core
From Core
From Core
(wdata2)
From Core
(wdata0)
From Core
(wdata3)
From Core
(wdata1)
Half-Rate Clock
from PLL
Write Clock
DFF
D
Q
OE Reg A
O
DFF
D
Q
OE Reg B
O
Double Data Rate
Output Registers
1
0
DQ or DQS
Data coming from the FPGA core are at half the frequency of the
memory interface clock frequency in half-rate mode
The full-rate write clock can come from the PLL. The DQ
write clock have a 90° offset to the DQS write clock.
OR2
TRI
Delay Chains
The Cyclone V devices contain run-time adjustable delay chains in the I/O blocks and the DQS logic blocks.
You can control the delay chain setting through the I/O or the DQS configuration block output.
Every I/O block contains a delay chain between the following elements:
• The output registers and output buffer
• The input buffer and input register
• The output enable and output buffer
• The R
T
OCT enable-control register and output buffer
You can bypass the DQS delay chain to achieve a 0° phase shift.
Altera Corporation
External Memory Interfaces in Cyclone V Devices
Send Feedback
6-27
Delay Chains
CV-52006
2013.05.06