Specifications

Figure 6-17: IOE Input Registers for Cyclone V Devices
Input Reg A
Input Reg B
D Q
Input Reg C
Double Data Rate Input Registers
Read FIFO
datain [1]
wrclk
rdclk
datain [0]
dataout[3..0]
To core
Half-rate or
full-rate clock
DQS/CQ
DQ
D
DFF
Q
D
DFF
Q D
DFF
Q
The input
clock can be
from the DQS
logic block or
from a global
clock line.
This half-rate or
full-rate read clock
comes from a PLL
through the clock
network
Output Registers
The Cyclone V output and output-enable path is divided into the HDR block, and output and output-enable
registers. The device can bypass each block of the output and output-enable path.
The output path is designed to route combinatorial or registered single data rate (SDR) outputs and full-rate
or half-rate DDR outputs from the FPGA core. Half-rate data is converted to full-rate with the HDR block,
clocked by the half-rate clock from the PLL.
The output-enable path has a structure similar to the output path—ensuring that the output-enable path
goes through the same delay and latency as the output path.
External Memory Interfaces in Cyclone V Devices
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Output Registers
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2013.05.06