Specifications

Figure 6-16: Dynamic OCT Control Block for Cyclone V Devices

DFF

OCT Control

OCT Half-Rate Clock

DFF

Write Clock

OCT Enable

OCT Control Path

The full-rate write clock comes from the PLL. The DQ write

clock and DQS write clock have a 90° offset between them

Related Information

Dynamic OCT in Cyclone V Devices on page 5-39

Provides more information about dynamic OCT control.

IOE Registers

The IOE registers are expanded to allow source-synchronous systems to have faster register-to-FIFO transfers

and resynchronization. All top, bottom, and right IOEs have the same capability.

Input Registers

The input path consists of the DDR input registers and the read FIFO block. You can bypass each block of

the input path.

There are three registers in the DDR input registers block. Registers A and B capture data on the positive

and negative edges of the clock while register C aligns the captured data. Register C uses the same clock as

The read FIFO block resynchronizes the data to the system clock domain and lowers the data rate to half

rate.

The following figure shows the registers available in the Cyclone V input path. For DDR3 and DDR2 SDRAM

interfaces, the DQS and DQSn signals must be inverted. If you use Altera’s memory interface IPs, the DQS

and DQSn signals are automatically inverted.

Altera Corporation

External Memory Interfaces in Cyclone V Devices

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IOE Registers

CV-52006

2013.05.06