Specifications

that any glitches on the DQS input signal during the end of a read operation and occurring while DQS is in
a postamble state do not affect the DQ IOE registers.
• For preamble state, the DQS is low, just after a high-impedance state.
• For postamble state, the DQS is low, just before it returns to a high-impedance state.
For external memory interfaces that use a bidirectional read strobe (DDR3 and DDR2 SDRAM), the DQS
signal is low before going to or coming from a high-impedance state.
Half Data Rate Block
The Cyclone V devices contain a half data rate (HDR) block in the postamble enable circuitry.
The HDR block is clocked by the half-rate resynchronization clock, which is the output of the I/O clock
divider circuit. There is an AND gate after the postamble register outputs to avoid postamble glitches from
a previous read burst on a non-consecutive read burst. This scheme allows half-a-clock cycle latency for
dqsenable assertion and zero latency for dqsenable deassertion.
Using the HDR block as the first stage capture register in the postamble enable circuitry block is optional.
Altera recommends using these registers if the controller is running at half the frequency of the I/Os.
Figure 6-15: Avoiding Glitch on a Non-Consecutive Read Burst Waveform
This figure shows how to avoid postamble glitches using the HDR block.
Delayed by
1/2T logic
Preamble
Postamble
Postamble glitch
DQS
Postamble Enable
dqsenable
Dynamic OCT Control
The dynamic OCT control block includes all the registers that are required to dynamically turn the on-chip
parallel termination (R
T
OCT) on during a read and turn R
T
OCT off during a write.
External Memory Interfaces in Cyclone V Devices
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Half Data Rate Block
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2013.05.06