Specifications

Update Enable Circuitry
The update enable circuitry enables the registers to allow enough time for the DQS delay settings to travel
from the DQS phase-shift circuitry or core logic to all the DQS logic blocks before the next change.
Both the DQS delay settings and the phase-offset settings pass through a register before going into the DQS
delay chains. The registers are controlled by the update enable circuitry to allow enough time for any changes
in the DQS delay setting bits to arrive at all the delay elements, which allows them to be adjusted at the same
time.
The circuitry uses the input reference clock or a user clock from the core to generate the update enable
output. The UniPHY intellectual property (IP) uses this circuit by default.
Figure 6-14: DQS Update Enable Waveform
This figure shows an example waveform of the update enable circuitry output.
Update Enable
Circuitry Output
System Clock
DQS Delay Settings
Updated every 8 cycles
DLL Counter Update
(Every 8 cycles)
7 bit
DLL Counter Update
(Every 8 cycles)
DQS Delay Chain
DQS delay chains consist of a set of variable delay elements to allow the input DQS signals to be shifted by
the amount specified by the DQS phase-shift circuitry or the logic array.
There are two delay elements in the DQS delay chain that have the same characteristics:
• Delay elements in the DQS logic block
• Delay elements in the DLL
The DQS pin is shifted by the DQS delay settings.
The number of delay chains required is transparent because the UniPHY IP automatically sets it when you
choose the operating frequency.
In Cyclone V E, GX, and GT devices, if you do not use the DLL to control the DQS delay chains, you can
input your own Gray-coded 7 bit settings using the delayctrlin[6..0] signals available in the UniPHY
IP.
In the Cyclone V SE, SX, and ST devices, the DQS delay chain is controlled by the DQS phase-shift circuitry
only.
DQS Postamble Circuitry
There are preamble and postamble specifications for both read and write operations in DDR3 and DDR2
SDRAM. The DQS postamble circuitry ensures that data is not lost if there is noise on the DQS line during
the end of a read operation that occurs while DQS is in a postamble state.
The Cyclone V devices contain dedicated postamble registers that you can control to ground the shifted
DQS signal that is used to clock the DQ input registers at the end of a read operation. This function ensures
Altera Corporation
External Memory Interfaces in Cyclone V Devices
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Update Enable Circuitry
CV-52006
2013.05.06