Specifications

Figure 6-12: PHYCLK Networks in Cyclone V SX C2, C4, C5, and C6 Devices, and Cyclone V ST D5 and D6
Devices
Left
PLL
Sub-BankSub-Bank
I/O Bank 7
Sub-BankSub-Bank
I/O Bank 8
PHYCLK Networks
HPS PHYCLK Networks
Left
PLL
Right
PLL
Sub-BankSub-Bank
I/O Bank 4
Sub-BankSub-Bank
I/O Bank 3
PHYCLK Networks
Transceiver Banks
HPS I/O
FPGA Device
HPS
PLL
HPS Block
Sub-BankSub-Bank
I/O Bank 5
PHYCLK Networks
DQS Logic Block
Each DQS/CQ/CQn/QK# pin is connected to a separate DQS logic block, which consists of the update enable
circuitry, DQS delay chains, and DQS postamble circuitry.
The following figure shows the DQS logic block.
Figure 6-13: DQS Logic Block in Cyclone V Devices
Update
Enable
Circuitry
7
7
7
7
dqsin
delayctrlin [6:0]
dqsupdateen
DQS Delay Chain
Bypass
7
dqsbusout
1
0
0
1
1
0
Input Reference
Clock
Postamble
Enable
dqsenablein
zerophaseclk
(Postamble clock)
dqsenableout
levelingclk
(Read-leveled postamble clock)
DQS Enable Control Circuit
DQS Pin
DQS Enable
dqsin
D
Q
PRE
0
1
dqsenable
D
Q
D
Q
D
Q
D
Q
DQS Postamble Circuitry
D Q
7
7
DQS delay settings from the DLL
delayctrlin [6:0]
2
DQS delay settings from the DLL
Core Logic
7
<dqs delay chain bypass>
enaphasetransferreg
0
1
2
<delay dqs enable>
dqsdisablen
This clock can come from a PLL
output clock or an input clock pin
Applicable only if the DQS
delay settings come from a
side with two DLLs
The dqsenable
signal can also
come from the
FPGA fabric
External Memory Interfaces in Cyclone V Devices
Altera Corporation
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CV-52006
DQS Logic Block
6-22
2013.05.06