Specifications

For the frequency range of each DLL frequency mode, refer to the device datasheet.
Related Information
Cyclone V Device Datasheet
PHY Clock (PHYCLK) Networks
The PHYCLK network is a dedicated high-speed, low-skew balanced clock tree designed for a high-
performance external memory interface.
The top and bottom sides of the Cyclone V devices have up to four PHYCLK networks each. There are up
to two PHYCLK networks on the left and right side I/O banks. Each PHYCLK network spans across one
I/O bank and is driven by one of the PLLs located adjacent to the I/O bank.
The following figures show the PHYCLK networks available in the Cyclone V devices.
Figure 6-8: PHYCLK Networks in Cyclone V E A2 and A4 Devices
Left
PLL
Right
PLL
Sub-BankSub-Bank
I/O Bank 7
Sub-BankSub-Bank
I/O Bank 8
PHYCLK Networks
Sub-BankSub-Bank
I/O Bank 4
Sub-BankSub-Bank
I/O Bank 3
PHYCLK Networks
Sub-Bank
I/O Bank 6
Sub-BankSub-Bank
I/O Bank 5
PHYCLK Networks
FPGA Device
Sub-Bank
Left
PLL
Right
PLL
Sub-Bank
I/O Bank 2
Sub-Bank
Sub-Bank
I/O Bank 1
PHYCLK Networks
Sub-Bank
External Memory Interfaces in Cyclone V Devices
Altera Corporation
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PHY Clock (PHYCLK) Networks
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2013.05.06