Specifications

Figure 6-6: DQS Pins and DLLs in Cyclone V SX (C2, C4, C5, and C6) and ST (D5 and D6) Devices
DQS Logic
Blocks
DLL
Reference
Clock
DLL
to
IOE
to
IOE
DLL
DQS
Pin
DQS
Pin
DQS
Pin
DQS
Pin
Transceiver Blocks
DLL
Reference
Clock
DLL
Reference
Clock
DLL
DLL
Δt
Δt
Δt
Δt
DQS Logic
Blocks
to
IOE
to
IOE
to
IOE
to
IOE
DQS
Pin
DQS
Pin
DQS
Pin
DQS
Pin
DQS
Pin
DQS
Pin
HPS I/O
Δt
Δt
Δt
Δt
DQS Logic
Blocks
to IOE
to IOE
ΔtΔt
to IOE
to IOE
HPS Block
HPS
PLL
Related Information
Cyclone V Device Pin-Out Files
Download the relevant pin tables from this web page.
Delay-Locked Loop
The delay-locked loop (DLL) uses a frequency reference to dynamically generate control signals for the delay
chains in each of the DQS pins, allowing the delay to compensate for process, voltage, and temperature
(PVT) variations. The DQS delay settings are Gray-coded to reduce jitter if the DLL updates the settings.
There are a maximum of four DLLs, located in each corner of the Cyclone V devices. You can clock each
DLL using different frequencies.
The DLLs can access the two adjacent sides from its location in the device. You can have two different
interfaces with the same frequency on the two sides adjacent to a DLL, where the DLL controls the DQS
delay settings for both interfaces.
Altera Corporation
External Memory Interfaces in Cyclone V Devices
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6-17
Delay-Locked Loop
CV-52006
2013.05.06