Specifications
Figure 6-4: DQS Pins and DLLs in Cyclone V E (A5, A7, and A9), GX (C4, C5, C7, and C9), GT (D5, D7, and
D9) Devices
DLL
Reference
Clock
Δt
Δt
Δt
Δt
DQS Logic
Blocks
DLL
Reference
Clock
DLL
to
IOE
to
IOE
to
IOE
to
IOE
DLL
DQS
Pin
DQS
Pin
DQS
Pin
DQS
Pin
Transceiver Blocks
DLL
Reference
Clock
DLL
Reference
Clock
DLL
DLL
Δt
Δt ΔtΔt
DQS Logic
Blocks
to
IOE
to
IOE
to
IOE
to
IOE
DQS
Pin
DQS
Pin
DQS
Pin
DQS
Pin
Δt Δt ΔtΔt
DQS Logic
Blocks
to
IOE
to
IOE
to
IOE
to
IOE
DQS
Pin
DQS
Pin
DQS
Pin
DQS
Pin
External Memory Interfaces in Cyclone V Devices
Altera Corporation
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CV-52006
DQS Phase-Shift Circuitry
6-16
2013.05.06