Specifications

Figure 6-1: External Memory Interface Datapath Overview for Cyclone V Devices
Memory
FPGA
DLL
4n
n
n
2n
DQ (Read)
DQ (Write)
Read FIFO
DQS (Read)
4n or 2n
4
DQS (Write)
DQS Write Clock
Half-Rate Clock
2n
2
DQ Write Clock
Postamble Enable
Postamble Clock
Full-Rate Clock
Note: There are slight block differences for different memory interface standards. The shaded blocks are part of the I/O elements.
Clock
Management
and Reset
DQS Delay
Chain
DQS
Enable
Circuit
DQS Enable
Control
Circuit
DQS Postamble
Circuitry
DDR Input
Registers
DDR Output
and Output
Enable
Registers
DDR Output
and Output
Enable
Registers
Half Data
Rate
Output
Registers
Half Data
Rate
Output
Registers
DQS Phase-Shift Circuitry
The Cyclone V DLL provides phase shift to the DQS pins on read transactions if the DQS pins are acting as
input clocks or strobes to the FPGA.
The following figures show how the DLLs are connected to the DQS pins in the various Cyclone V variants.
The reference clock for each DLL may come from adjacent PLLs.
The following figures show all possible connections for each device. For available pins and connections
in each device package, refer to the device pin-out files.
Note:
Altera Corporation
External Memory Interfaces in Cyclone V Devices
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6-13
DQS Phase-Shift Circuitry
CV-52006
2013.05.06