Specifications

The following device features are available for external memory interfaces:
• DQS phase-shift circuitry
• PHY Clock (PHYCLK) networks
• DQS logic block
• Dynamic on-chip termination (OCT) control
• IOE registers
• Delay chains
• Hard memory controllers
UniPHY IP
The high-performance memory interface solution includes the self-calibrating UniPHY IP that is optimized
to take advantage of the Cyclone V I/O structure and the Quartus II software TimeQuest Timing Analyzer.
The UniPHY IP helps set up the physical interface (PHY) best suited for your system. This provides the total
solution for the highest reliable frequency of operation across process, voltage, and temperature (PVT)
variations.
The UniPHY IP instantiates a PLL to generate related clocks for the memory interface. The UniPHY IP can
also dynamically choose the number of delay chains that are required for the system. The amount of delay
is equal to the sum of the intrinsic delay of the delay element and the product of the number of delay steps
and the value of the delay steps.
The UniPHY IP and the Altera memory controller MegaCore
®
functions can run at half the I/O interface
frequency of the memory devices, allowing better timing management in high-speed memory interfaces.
The Cyclone V devices contain built-in circuitry in the IOE to convert data from full rate (the I/O frequency)
to half rate (the controller frequency) and vice versa.
Related Information
Reference Material volume, External Memory Interface Handbook
Provides more information about the UniPHY IP.
External Memory Interface Datapath
The following figure shows an overview of the memory interface datapath that uses the Cyclone V I/O
elements. In the figure, the DQ/DQS read and write signals may be bidirectional or unidirectional, depending
on the memory standard. If the signal is bidirectional, it is active during read and write operations. You can
bypass each register block.
External Memory Interfaces in Cyclone V Devices
Altera Corporation
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UniPHY IP
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2013.05.06