Specifications

External Memory Performance
Table 6-2: External Memory Interface Performance in Cyclone V Devices
The maximum and minimum operating frequencies depend on the memory interface standards and the supported
delay-locked loop (DLL) frequency listed in the device datasheet.
Minimum Frequency (MHz)
Maximum Frequency (MHz)
Voltage
(V)
Interface
Soft ControllerHard Controller
3003004001.5
DDR3 SDRAM
3003004001.35
1673004001.8DDR2 SDRAM
1673003331.2LPDDR2 SDRAM
Related Information
Cyclone V Device Datasheet
HPS External Memory Performance
Table 6-3: HPS External Memory Interface Performance
The hard processor system (HPS) is available in Cyclone V SoC FPGA devices only.
HPS Hard Controller (MHz)Voltage (V)Interface
4001.5
DDR3 SDRAM
4001.35
4001.8
DDR2 SDRAM
4001.5
3331.2LPDDR2 SDRAM
Memory Interface Pin Support in Cyclone V Devices
In the Cyclone V devices, the memory interface circuitry is available in every I/O bank that does not support
transceivers. The devices offer differential input buffers for differential read-data strobe and clock operations.
The memory clock pins are generated with double data rate input/output (DDRIO) registers.
Related Information
Planning Pin and FPGA Resources chapter, External Memory Interface Handbook
Provides more information about which pins to use for memory clock pins and pin location requirements.
External Memory Interfaces in Cyclone V Devices
Altera Corporation
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External Memory Performance
6-2
2013.05.06