Specifications

Figure 5-45: RSKM Equation
Conventions used for the equation:
RSKMthe timing margin between the receivers clock input and the data input sampling window.
Time unit interval (TUI)time period of the serial data.
SWthe period of time that the input data must be stable to ensure that data is successfully sampled by
the LVDS receiver. The SW is a device property and varies with device speed grade.
TCCSthe timing difference between the fastest and the slowest output edges, including t
CO
variation
and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement.
You must calculate the RSKM value to decide whether the LVDS receiver can sample the data properly or
not, given the data rate and device. A positive RSKM value indicates that the LVDS receiver can sample the
data properly, whereas a negative RSKM indicates that it cannot sample the data properly.
The following figure shows the relationship between the RSKM, TCCS, and the SW of the receiver.
Figure 5-46: Differential High-Speed Timing Diagram and Timing Budget for LVDS Mode
TUI
Time Unit Interval (TUI)
TCCS
Internal
Clock
Falling Edge
t
SW
(min)
Bit n
t
SW
(max)
Bit n
TCCS
TCCS
2
Receiver
Input Data
Transmitter
Output Data
Internal
Clock
Synchronization
External
Clock
Receiver
Input Data
Internal
Clock
External
Input Clock
Timing Budget
Timing Diagram
Clock Placement
SW
TCCS
RSKM RSKM
SW
RSKM RSKM
Altera Corporation
I/O Features in Cyclone V Devices
Send Feedback
5-71
Receiver Skew Margin for LVDS Mode
CV-52005
2013.06.21