Specifications

Figure 5-39: Receiver Data Realignment Rollover
This figure shows a preset value of four bit-times before rollover occurs. The rx_cda_max signal pulses
for one rx_outclock cycle to indicate that rollover has occurred.
rx_inclock
rx_channel_data_align
rx_outclock
rx_cda_max
Deserializer
You can statically set the deserialization factor to x4, x5, x6, x7, x8, x9, or x10 by using the Quartus II software.
You can bypass the deserializer in the Quartus II MegaWizard Plug-In Manager to support DDR (x2) or
SDR (x1) operations, as shown in the following figure.
Figure 5-40: Deserializer Bypass
rx_in
IOE supports SDR, DDR, or non-registered datapath
LVDS Receiver
FPGA
Fabric
rx_out
Bit SlipDeserializer
rx_inclock / tx_inclock
DOUTDOUT
DIN
Fractional PLL
(LOAD_EN,
diffioclk)
2
10
3
(LVDS_LOAD_EN,
LVDS_diffioclk, rx_outclock)
diffioclk
rx_outclock
DIN
+
–
IOE
10
2
Note: Disabled blocks and signals are grayed out
The IOE contains two data input registers that can operate in DDR or SDR mode. In DDR mode,
rx_inclock clocks the IOE register. In SDR mode, data is directly passed through the IOE. In SDR and
DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
Receiver Mode in Cyclone V Devices
The Cyclone V devices support the LVDS receiver mode.
LVDS Receiver Mode
Input serial data is registered at the rising edge of the serial LVDS_diffioclk clock that is produced by
the left and right PLLs.
I/O Features in Cyclone V Devices
Altera Corporation
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CV-52005
Deserializer
5-66
2013.06.21