Specifications

Figure 5-37: Receiver Block Diagram
rx_in
Bit SlipDeserializer
rx_inclock / tx_inclock
IOE supports SDR, DDR, or non-registered datapath
LVDS Receiver
FPGA
Fabric
rx_out
rx_outclock
LVDS Clock Domain
DOUT
DIN
DOUT
DIN
Fractional PLL
+
–
IOE
(LOAD_EN,
diffioclk)
2
10
10
3
(LVDS_LOAD_EN,
LVDS_diffioclk, rx_outclock)
2
diffioclk
10 bits
maxiumum
data width
Data Realignment Block (Bit Slip)
Skew in the transmitted data along with skew added by the link causes channel-to-channel skew on the
received serial data streams. To compensate for this channel-to-channel skew and establish the correct
received word boundary at each channel, each receiver channel has a dedicated data realignment circuit that
realigns the data by inserting bit latencies into the serial stream.
An optional RX_CHANNEL_DATA_ALIGN port controls the bit insertion of each receiver independently
controlled from the internal logic. The data slips one bit on the rising edge of RX_CHANNEL_DATA_ALIGN.
The requirements for the RX_CHANNEL_DATA_ALIGN signal include the following items:
• The minimum pulse width is one period of the parallel clock in the logic array.
• The minimum low time between pulses is one period of the parallel clock.
• The signal is an edge-triggered signal.
•
The valid data is available two parallel clock cycles after the rising edge of RX_CHANNEL_DATA_ALIGN.
Figure 5-38: Data Realignment Timing
This figure shows receiver output (RX_OUT) after one bit slip pulse with the deserialization factor set to 4.
rx_inclock
rx_in
rx_outclock
rx_channel_data_align
rx_out
3 2 1 0 3 2 1 0 3 2 1 0
3210 321x xx21 0321
The data realignment circuit can have up to 11 bit-times of insertion before a rollover occurs. The
programmable bit rollover point can be from 1 to 11 bit-times, independent of the deserialization factor.
Set the programmable bit rollover point equal to, or greater than, the deserialization factor—allowing enough
depth in the word alignment circuit to slip through a full word. You can set the value of the bit rollover point
using the MegaWizard Plug-In Manager. An optional status port, RX_CDA_MAX, is available to the FPGA
fabric from each channel to indicate the reaching of the preset rollover point.
Altera Corporation
I/O Features in Cyclone V Devices
Send Feedback
5-65
Data Realignment Block (Bit Slip)
CV-52005
2013.06.21