Specifications

The following tables list the number of true LVDS buffers supported in Cyclone V devices with these
conditions:
• The LVDS channel count does not include dedicated clock pins.
• Each I/O sub-bank can support up to two independent ALTLVDS interfaces. For example, you can place
two ALTLVDS interfaces in bank 8A driven by two different PLLs, provided that the LVDS channels are
not interleaved.
Table 5-35: LVDS Channels Supported in Cyclone V E Devices—Preliminary
RXTXSidePackageMember Code
88Top
256-pin FineLine BGA
A2 and A4
44Left
88Right
1212Bottom
1212Top
324-pin Ultra FineLine BGA
88Left
88Right
1616Bottom
1915Top
383-pin Micro FineLine BGA
1212Left
87Right
2016Bottom
2020Top
484-pin Ultra FineLine BGA
44Left
88Right
2424Bottom
2020Top
484-pin FineLine BGA
44Left
88Right
2424Bottom
Altera Corporation
I/O Features in Cyclone V Devices
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True LVDS Buffers in Cyclone V Devices
CV-52005
2013.06.21