Specifications

Figure 5-28: High-Speed Differential I/O Locations in Cyclone V E A2 and A4 Devices
FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
General Purpose I/O and High-Speed
LVDS I/O with SERDES
Fractional PLL
Figure 5-29: High-Speed Differential I/O Locations in Cyclone V GX C3 Devices
FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
Fractional PLL
Transceiver Block
General Purpose I/O and High-Speed
LVDS I/O with SERDES
Figure 5-30: High-Speed Differential I/O Locations in Cyclone V GX C4, C5, C7, and C9 Devices, and Cyclone V
GT D5, D7, and D9 Devices
Fractional PLL
Transceiver Block
FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
General Purpose I/O and High-Speed
LVDS I/O with SERDES
I/O Features in Cyclone V Devices
Altera Corporation
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CV-52005
High-Speed Differential I/O Locations
5-52
2013.06.21