Specifications

Figure 5-27: LVPECL DC-Coupled Termination
Z
0
= 50 Ω
Z
0
= 50 Ω
100 Ω
LVPECL
Output Buffer
LVPECL
Input Buffer
For information about the V
ICM
specification, refer to the device datasheet.
Related Information
Cyclone V Device Datasheet
Dedicated High-Speed Circuitries
The Cyclone V device has dedicated circuitries for differential transmitter and receiver to transmit or receive
high-speed differential signals.
Table 5-34: Features and Dedicated Circuitries of the Differential Transmitter and Receiver
Differential ReceiverDifferential TransmitterFeature
LVDS, SLVS, mini-LVDS, and RSDSLVDS, mini-LVDS, and RSDSTrue differential buffer
Up to 10 bit deserializerUp to 10 bit serializerSERDES
Generates different phases of a clock for data
synchronizer
Clocks the load and shift
registers
Fractional PLL
—StaticProgrammable V
OD
—Boosts output currentProgrammable pre-emphasis
Inserts bit latencies into serial data—Data realignment block (Bit-
slip)
Manual—Skew adjustment
100 Ω in LVDS and SLVS standards—On-chip termination (OCT)
Related Information
Guideline: Use PLLs in Integer PLL Mode for LVDS on page 5-12
High-Speed Differential I/O Locations
The following figures show the locations of the dedicated serializer/deserializer (SERDES) circuitry and the
high-speed I/Os in the Cyclone V devices.
Altera Corporation
I/O Features in Cyclone V Devices
Send Feedback
5-51
Dedicated High-Speed Circuitries
CV-52005
2013.06.21