Specifications

Figure 5-25: Resistor Network Calculation
Altera recommends that you perform additional simulations with IBIS or SPICE models to validate
that the custom resistor values meet the RSDS or mini-LVDS I/O standard requirements.
Note:
For information about the data rates supported for external single resistor or three-resistor network, refer
to the device datasheet.
Related Information
• Cyclone V Device Datasheet
• National Semiconductor (www.national.com)
For more information about the RSDS I/O standard, refer to the RSDS Specification on the National
Semiconductor web site.
LVPECL Termination
The Cyclone V devices support the LVPECL I/O standard on input clock pins only:
• LVPECL input operation is supported using LVDS input buffers.
• LVPECL output operation is not supported.
Use AC coupling if the LVPECL common-mode voltage of the output buffer does not match the LVPECL
input common-mode voltage.
Altera recommends that you use IBIS models to verify your LVPECL AC/DC-coupled termination.Note:
Figure 5-26: LVPECL AC-Coupled Termination
Z
0
= 50 Ω
V
ICM
Z
0
= 50 Ω
50 Ω
50 Ω
0.1 µF
0.1 µF
LVPECL
Output Buffer
LVPECL
Input Buffer
Support for DC-coupled LVPECL is available if the LVPECL output common mode voltage is within the
Cyclone V LVPECL input buffer specification.
I/O Features in Cyclone V Devices
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LVPECL Termination
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2013.06.21