Specifications

Figure 1-4: LAB-Wide Control Signals for Cyclone V Devices
This figure shows the clock sources and clock enable signals in a LAB.
Dedicated Row
LAB Clocks
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclk2
syncload
labclkena0
or asyncload
or labpreset
labclk0
labclk1
labclr1
labclkena1 labclkena2 labclr0 synclr
6
6
6
There are two unique
clock signals per LAB.
ALM Resources
One ALM contains four programmable registers. Each register has the following ports:
• Data
• Clock
• Synchronous and asynchronous clear
• Synchronous load
Global signals, general-purpose I/O (GPIO) pins, or any internal logic can drive the clock and clear control
signals of an ALM register.
GPIO pins or internal logic drives the clock enable signal.
For combinational functions, the registers are bypassed and the output of the look-up table (LUT) drives
directly to the outputs of an ALM.
The Quartus II software automatically configures the ALMs for optimized performance.Note:
Altera Corporation
Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices
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ALM Resources
CV-52001
2013.05.06