Specifications

Figure 5-20: HSTL I/O Standard Termination
This figure shows the details of HSTL I/O termination on the Cyclone V devices.
Transmitter Receiver
50 Ω
V
REF
V
REF
V
REF
V
REF
Series
OCT 50 Ω
FPGA
Parallel OCT
100 Ω
100 Ω
GND
50 Ω
V
CCIO
100 Ω
100 Ω
GND
V
CCIO
Series
OCT 25 Ω
100 Ω
100 Ω
GND
50 Ω
V
CCIO
100 Ω
100 Ω
GND
V
CCIO
100 Ω
100 Ω
GND
V
CCIO
Transmitter Receiver
50 Ω
V
REF
Series OCT 50 Ω
Transmitter Receiver
50 Ω
50 Ω
V
REF
V
TT
V
REF
FPGA
Parallel OCT
100 Ω
100 Ω
GND
V
CCIO
50 Ω
V
TT
Transmitter Receiver
50 Ω
V
REF
Series OCT 25 Ω
50 Ω
V
TT
50 Ω
V
TT
Transmitter Receiver
50 Ω
V
REF
50 Ω
V
TT
Transmitter Receiver
50 Ω
V
REF
50 Ω
V
TT
50 Ω
V
TT
FPGA FPGA FPGA FPGA
HSTL Class ITermination
OCT Transmit
OCT Receive
HSTL Class II
OCT in
Bidirectional
Pins
External
On-Board
Termination
Series
OCT 50 Ω
Series
OCT 25 Ω
Related Information
Dynamic OCT in Cyclone V Devices on page 5-39
Differential I/O Termination
The I/O pins are organized in pairs to support differential I/O standards. Each I/O pin pair can support
differential input and output buffers.
The supported I/O standards such as Differential SSTL-15, Differential SSTL-125, and Differential SSTL-
135 typically do not require external board termination.
Altera recommends that you use dynamic OCT with these I/O standards to save board space and cost.
Dynamic OCT reduces the number of external termination resistors used.
Differential HSTL, SSTL, and HSUL Termination
Differential HSTL, SSTL, and HSUL inputs use LVDS differential input buffers. However, R
D
support is
only available if the I/O standard is LVDS.
Differential HSTL, SSTL, and HSUL outputs are not true differential outputs. These I/O standards use two
single-ended outputs with the second output programmed as inverted.
I/O Features in Cyclone V Devices
Altera Corporation
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CV-52005
Differential I/O Termination
5-46
2013.06.21