Specifications

Figure 5-19: SSTL I/O Standard Termination
This figure shows the details of SSTL I/O termination on Cyclone V devices.
Transmitter Receiver
50 Ω
25 Ω
25 Ω
Series
OCT 50 Ω
Series
OCT 50 Ω
FPGA
Parallel OCT
100 Ω
100 Ω
GND
FPGA FPGA FPGA FPGA
50 Ω
V
CCIO
V
CCIO
V
CCIO
V
CCIO
V
CCIO
V
CCIO
100 Ω
100 Ω
GND
Series
OCT 25 Ω
Series
OCT 25 Ω
100 Ω
100 Ω
GND
50 Ω
100 Ω
100 Ω
GND
100 Ω
100 Ω
GND
Transmitter Receiver
50 Ω
Series OCT 50 Ω
Transmitter Receiver
50 Ω
50 Ω
25 Ω
FPGA
Parallel OCT
100 Ω
100 Ω
GND
50 Ω
Transmitter Receiver
50 Ω
Series OCT 25 Ω
50 Ω
50 Ω
Transmitter Receiver
50 Ω
V
REF
V
REF
V
REF
V
REF
V
REF
V
REF
50 Ω
V
TT
V
TT
V
TT
V
TT
V
TT
V
TT
V
TT
Transmitter Receiver
50 Ω
50 Ω
50 Ω
25 Ω
V
REF
V
REF
V
REF
V
REF
SSTL Class ITermination
OCT Transmit
OCT Receive
SSTL Class II
External
On-Board
Termination
OCT in
Bidirectional
Pins
Altera Corporation
I/O Features in Cyclone V Devices
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5-45
Single-ended I/O Termination
CV-52005
2013.06.21