Specifications

Figure 5-15: Dynamic R
T
OCT in Cyclone V Devices
TransmitterReceiver
50 Ω
100 Ω
100 Ω
50 Ω
GND
Transmitter Receiver
FPGA OCT FPGA OCT
Z
0
= 50 Ω
V
CCIO
100 Ω
100 Ω
GND
V
CCIO
50 Ω
100 Ω
100 Ω
50 Ω
GND
FPGA OCT FPGA OCT
Z
0
= 50 Ω
V
CCIO
100 Ω
100 Ω
GND
V
CCIO
Related Information
On-Chip I/O Termination in Cyclone V Devices on page 5-33
LVDS Input R
D
OCT in Cyclone V Devices
The Cyclone V devices support R
D
OCT in all I/O banks.
You can use R
D
OCT if you set the V
CCPD
to 2.5 V.
Figure 5-16: Differential Input OCT
The Cyclone V devices support OCT for differential LVDS and SLVS input buffers with a nominal resistance
value of 100 Ω, as shown in this figure.
100 Ω
ReceiverTransmitter
Z
0
= 50 Ω
Z
0
= 50 Ω
Related Information
On-Chip I/O Termination in Cyclone V Devices on page 5-33
I/O Features in Cyclone V Devices
Altera Corporation
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CV-52005
LVDS Input R
D
OCT in Cyclone V Devices
5-40
2013.06.21