Specifications

Calibrated OCT (Input)
I/O Standard
RZQ (Ω)R
T
(Ω)
(12)
24020, 30, 40, 60, 120Differential SSTL-125
The R
T
OCT calibration circuit compares the total impedance of the I/O buffer to the external resistor
connected to the RZQ pin. The circuit dynamically enables or disables the transistors until the total impedance
of the I/O buffer matches the external resistor.
Calibration occurs at the end of the device configuration. When the calibration circuit finds the correct
impedance, the circuit powers down and stops changing the characteristics of the drivers.
Figure 5-14: R
T
OCT with Calibration
Transmitter
Receiver
FPGA OCT
GND
100 Ω
100 Ω
Z
0
= 50 Ω
V
REF
V
CCIO
Related Information
On-Chip I/O Termination in Cyclone V Devices on page 5-33
Dynamic OCT in Cyclone V Devices
Dynamic OCT is useful for terminating a high-performance bidirectional path by optimizing the signal
integrity depending on the direction of the data. Dynamic OCT also helps save power because device
termination is internal—termination switches on only during input operation and thus draw less static
power.
If you use the SSTL-15, SSTL-135, and SSTL-125 I/O standards with the DDR3 memory interface,
Altera recommends that you use dynamic OCT with these I/O standards to save board space and
cost. Dynamic OCT reduces the number of external termination resistors used.
Note:
Table 5-32: Dynamic OCT Based on Bidirectional I/O
Dynamic R
T
OCT or R
S
OCT is enabled or disabled based on whether the bidirectional I/O acts as a receiver or
driver.
StateBidirectional I/ODynamic OCT
EnabledActs as a receiver
Dynamic R
T
OCT
DisabledActs as a driver
DisabledActs as a receiver
Dynamic R
S
OCT
EnabledActs as a driver
(12)
Final values are pending silicon characterization.
Altera Corporation
I/O Features in Cyclone V Devices
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5-39
Dynamic OCT in Cyclone V Devices
CV-52005
2013.06.21