Specifications

Programmable Current Strength
You can use the programmable current strength to mitigate the effects of high signal attenuation that is
caused by a long transmission line or a legacy backplane.
Table 5-25: Programmable Current Strength Settings for Cyclone V Devices
The output buffer for each Cyclone V device I/O pin has a programmable current strength control for the I/O
standards listed in this table.
Supported in HPS
(SoC FPGA Devices Only)
I
OH
/ I
OL
Current Strength Setting (mA)
(Default setting in bold)
I/O Standard
Yes (except 16 mA)16, 8, 43.3 V LVTTL
Yes23.3 V LVCMOS
Yes16, 12, 8, 43.0 V LVTTL
Yes16, 12, 8, 43.0 V LVCMOS
Yes16, 12, 8, 42.5 V LVCMOS
Yes12, 10, 8, 6, 4, 21.8 V LVCMOS
Yes12, 10, 8, 6, 4, 21.5 V LVCMOS
—8, 6, 4, 21.2 V LVCMOS
—12, 10, 8SSTL-2 Class I
—16SSTL-2 Class II
Yes12, 10, 8, 6, 4SSTL-18 Class I
Yes16SSTL-18 Class II
Yes12, 10, 8, 6, 4SSTL-15 Class I
Yes16SSTL-15 Class II
—12, 10, 8, 6, 41.8 V HSTL Class I
—161.8 V HSTL Class II
Yes12, 10, 8, 6, 41.5 V HSTL Class I
Yes161.5 V HSTL Class II
—12, 10, 8, 6, 41.2 V HSTL Class I
—161.2 V HSTL Class II
Altera recommends that you perform IBIS or SPICE simulations to determine the best current
strength setting for your specific application.
Note:
Related Information
Programmable IOE Features in Cyclone V Devices on page 5-28
Altera Corporation
I/O Features in Cyclone V Devices
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5-29
Programmable Current Strength
CV-52005
2013.06.21