Specifications

I/O Buffer and Registers in Cyclone V Devices
I/O registers are composed of the input path for handling data from the pin to the core, the output path for
handling data from the core to the pin, and the output enable (OE) path for handling the OE signal to the
output buffer. These registers allow faster source-synchronous register-to-register transfers and resynchro-
nization.
Table 5-23: Input and Output Paths in Cyclone V Devices
This table summarizes the input and output path in the Cyclone V devices.
Output PathInput Path
Consists of:
•
Output or OE registers
• Alignment registers
• Half data rate blocks
Consists of:
• DDR input registers
• Alignment and synchronization registers
• Half data rate blocks
You can bypass each block of the output and OE paths.
You can bypass each block in the input path. The
input path uses the deskew delay to adjust the input
register clock delay across process, voltage, and
temperature (PVT) variations.
Figure 5-9: IOE Structure for Cyclone V Devices
This figure shows the Cyclone V FPGA IOE structure. In the figure, one dynamic on-chip termination (OCT)
control is available for each DQ/DQS group.
4
Open Drain
On-Chip
Termination
Bus-Hold
Circuit
Programmable
Current
Strength and
Slew Rate
Control
V
CCIO
Programmable
Pull-Up Resistor
Half Data
Rate Block
Write
Data
from
Core
4
PRN
D Q
PRN
D Q
PRN
D Q
PRN
D Q
PRN
D Q
OE Register
OE Register
Output Register
Output Register
clkout
To
Core
To
Core
D5 Delay
Input Register
PRN
D
Q
Input Register
PRN
D
Q
Input Register
clkin
D5 Delay
Read
Data
to
Core
From OCT
Calibration
Block
D3_0
Delay
D3_1
Delay
D1
Delay
Output Buffer
Input Buffer
D5_OCT
From Core
DQS Logic Block
Dynamic OCT Control
D4 Delay
DQS
CQn
Read
FIFO
2
OE
from
Core
Half Data
Rate Block
Same avalaible settings in
the Quartus II software
Altera Corporation
I/O Features in Cyclone V Devices
Send Feedback
5-27
I/O Buffer and Registers in Cyclone V Devices
CV-52005
2013.06.21