Specifications

Connection between Altera_PLL and ALTLVDS
Figure 5-4: LVDS Interface with the Altera_PLL Megafunction
This figure shows the connections between the Altera_PLL and ALTLVDS megafunction.
D Q
D
Q
Transmitter
Core Logic
tx_coreclk
LVDS Transmitter
(ALTLVDS)
LVDS Receiver
(ALTLVDS)
rx_inclock
Receiver
Core Logic
rx_coreclk
rx_enable
pll_areset
rx_out
tx_inclock
tx_enable
tx_in
Altera_PLL
inclk0
pll_areset
outclk0
outclk2
outclk1
locked
FPGA Fabric
When generating the Altera_PLL megafunction, the Left/Right PLL option is configured to set up the PLL
in LVDS mode. Instantiation of pll_areset is optional.
Guideline: Use the Same V
CCPD
for All I/O Banks in a Group
In the Cyclone V GX and GT devices, all I/O banks have individual V
CCPD
pin except the following I/O bank
groups, which share one V
CCPD
pin in each group:
• Bank 3B and 4A
• Bank 7A and 8A
Examples:
• If bank 3B uses a 3.0 V V
CCPD
, bank 4A must also use 3.0 V V
CCPD
.
• If bank 8A uses a 2.5 V V
CCPD
, bank 7A must also use 2.5 V V
CCPD
.
For more information about the I/O banks available in each device package, refer to the related links.
Related Information
• Modular I/O Banks for Cyclone V E Devices on page 5-21
• Modular I/O Banks for Cyclone V GX Devices on page 5-22
• Modular I/O Banks for Cyclone V GT Devices on page 5-23
• Modular I/O Banks for Cyclone V SE Devices on page 5-24
• Modular I/O Banks for Cyclone V SX Devices on page 5-25
• Modular I/O Banks for Cyclone V ST Devices on page 5-26
Altera Corporation
I/O Features in Cyclone V Devices
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5-17
Connection between Altera_PLL and ALTLVDS
CV-52005
2013.06.21