Specifications

Related Information
LVDS SERDES Transmitter/Receiver (ALTLVDS_RX/TX) Megafunction User Guide
More information about the different clocking requirement for soft SERDES.
Altera_PLL Parameter Values for External PLL Mode
The following example shows the clocking requirements to generate output clocks for ALTLVDS_TX and
ALTLVDS_RX using the Altera_PLL megafunction. The examples set the phase shift with the assumption
that the clock and data are edge aligned at the pins of the device.
For other clock and data phase relationships, Altera recommends that you first instantiate your
ALTLVDS_RX and ALTLVDS_TX interface without using the external PLL mode option. Compile
Note:
the megafunctions in the Quartus II software and take note of the frequency, phase shift, and duty
cycle settings for each clock output. Enter these settings in the Altera_PLL megafunction parameter
editor and then connect the appropriate output to the ALTLVDS_RX and ALTLVDS_TX
megafunctions.
Table 5-13: Example: Generating Output Clocks Using an Altera_PLL Megafunction
This table lists the parameter values that you can set in the Altera_PLL parameter editor to generate three output
clocks using an Altera_PLL megafunction if you are not using DPA and soft-CDR mode.
outclk2
(Used as the core clock for the
parallel data registers for both
transmitter and receiver)
outclk1
(Connects to the tx_enable
port of ALTLVDS_TX and the
rx_enable port of
ALTLVDS_RX)
outclk0
(Connects to the tx_
inclock port of ALTLVDS_
TX and the rx_inclock
port of ALTLVDS_RX)
Parameter
data rate/serialization
factor
data rate/serialization factordata rateFrequency
–180/serialization factor
(outclk0 phase shift
divided by the serialization
factor)
[(deserialization factor – 2)/
deserialization factor] x 360°
–180°Phase shift
50%100/serialization factor50%Duty cycle
I/O Features in Cyclone V Devices
Altera Corporation
Send Feedback
CV-52005
Altera_PLL Parameter Values for External PLL Mode
5-16
2013.06.21