Specifications

Table 5-11: Reference Clock Pin for I/O Bank Without Dedicated Reference Clock Pin
Reference Clock Pin I/O BankData Channel I/O BankMember CodeDevice Variant
4ABanks using bottom
right PLL
A2, A4
Cyclone V E
3BBanks using bottom
left PLL
7ABanks using top right
PLL
8ABanks using top left
PLL
3B3A
A5, A9
5B5A
5B5AA7
3B3A
C4, C5, C9
Cyclone V GX 5B5A
5B5AC3, C7
3B3A
D5, D9
Cyclone V GT 5B5A
3B3AD7
3B3A
A2, A4
Cyclone V SE 5B5A
5B5AA5, A6
3B3A
C2, C4
Cyclone V SX 5B5A
5B5AC5, C6
5B5AD5, D6Cyclone V ST
Guideline: Using LVDS Differential Channels
If you use LVDS channels, adhere to the following guidelines.
LVDS Channel Driving Distance
Each PLL can drive all the LVDS channels in the entire quadrant.
Using Both Corner PLLs
You can use both corner PLLs to drive LVDS channels simultaneously. You can use a corner PLL to drive
all the transmitter channels and the other corner PLL to drive all the receiver channels in the same I/O bank.
Altera Corporation
I/O Features in Cyclone V Devices
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5-13
Guideline: Using LVDS Differential Channels
CV-52005
2013.06.21