Specifications

Page 4 Overview of the Design Security Feature
Using the Design Security Features in Altera FPGAs June 2012 Altera Corporation
c Enabling the tamper-protection bit disables the test mode in FPGAs. Disabling the test
mode is irreversible and prevents Altera from carrying out failure analysis. To enable
the tamper-protection bit, contact Altera Technical Support.
f For more information about the available security modes in the 40-nm and the 28-nm
FPGAs, refer to the Configuration, Design Security, and Remote System Upgrades chapter
of the respective device handbook.
Key Programming
Table 4 lists the four different methods for key programming.
Key programming uses the following definitions:
■ On-board: procedure in which the device is programmed on your board
■ Off-board: procedure in which the device is programmed on a separate
programming system
■ Prototyping: method initially used to verify proper operation of a particular
method
■ Production: method used for large-volume production
Table 4. Key Programming Methods
(1)
Programming Procedure Method Programming Tool
On-Board Programming
Prototyping
EthernetBlaster, JTAG
technologies, ByteBlaster
™
II,
USB-Blaster
™
(2)
Production JTAG technologies
Off-Board Programming
Prototyping System General
(3)
Production System General
(3)
Notes to Table 4:
(1) For information about programming support, contact Altera Technical Support.
(2) ByteBlaster II and USB-Blaster support only volatile key programming. EthernetBlaster and JTAG technologies
support both volatile and non-volatile key programming. For non-volatile key programming, you must regulate the
JTAG TCK pulse width (period) for proper poly-fuse programming.
(3) For 28-nm FPGAs, design security key programming support with System General tool is still pending availability
but is available for 40-nm FPGAs.